The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and a semiconductor integrated circuit.
In recent years, a highly integrated semiconductor memory device (memory LSI) has been increasingly demanded to operate at a higher rate with reduced power consumption. As a highly integrated semiconductor memory device which can electrically write and erase data, a flash EEPROM (electrically erasable programmable read only memory) has been widely used.
FIG. 14D shows the cross section of a conventional flash EEPROM. The flash EEPROM will be described with reference to the method for fabricating the same.
First, as shown in FIG. 14A, after a gate oxide film 102 has been formed by oxidizing the surface of a semiconductor substrate 101, a poly-silicon film 130 including a portion to be a floating gate 103 is deposited thereon. Next, a silicon nitride film 131 is deposited on the poly-silicon film 130, and an opening is provided through a region defining the position and the shape of the floating gate 103 by performing a commonly used photolithography process on the silicon nitride film 131. Next, the exposed surface of the poly-silicon film 130 is selectively oxidized by using the silicon nitride film 131 having such an opening as a mask, thereby forming an oxide film 104 on the poly-silicon film 130.
Next, after the silicon nitride film 131 has been removed, the poly-silicon film 130 is patterned, thereby forming the floating gate 103 as shown in FIG. 14B. The oxide film 104 is formed on the floating gate 103. The film thickness of the peripheral region of the floating gate 103 becomes larger than that of the center region thereof. In other words, the floating gate 103 has a sharpened peripheral region, which shape is affected by a Bird's Peak generated by the formation of the oxide film 104.
Subsequently, as shown in FIG. 14C, the sides of the floating gate 103 are oxidized, thereby forming a second gate oxide film 107. Thereafter, a control gate 109 is formed so as to overlap the floating gate 103.
Finally, as shown in FIG. 14D, impurity ions are implanted into the substrate 101, thereby forming a drain region 112 and a source region 113.
The write of data is performed by accelerating the electrons from the source region 113 by a high electric field formed between the floating gate 103 and the control gate 109 and by injecting the electrons into the floating gate 103. The erasure of data is performed by taking out the electrons, which have been accumulated in the floating gate 103, from the floating gate 103 into the control gate 109 upon the application of a positive voltage to the control gate 109. Since the peripheral region of the floating gate 103 has a sharpened shape as described above, the electric field is concentrated in the peripheral region. Thus, the electrons can be taken out more easily.
However, the above-described structure has the following problems.
First, the flash EEPROM has a problem in that the data write speed thereof is lower than that of a DRAM by two orders of magnitude. Such a low data write speed necessarily requires increasing the voltages (i.e., a drain voltage and a gate voltage) for writing data. As a result, the circuit configuration and the fabrication process thereof are complicated. In other words, it is very difficult to improve both a write speed and write voltages. This is because, in order to increase such a very low write speed, there is no other means than setting the voltages at high values. For example, when a control gate voltage is set at about 9 V and a drain voltage is set at about 4.5 V for writing data, a write time, required for varying an inverted voltage necessary for reading, should be at least as long as 10 .mu.s.
One of the reasons for such a long write time is poor efficiency with which channel hot electrons are injected into the floating gate. In writing data, in a conventional flash EEPROM, the channel hot electrons are scattered to be oriented in all the directions. However, since an electric field is applied in the direction from the source toward the drain, the velocities of the channel hot electrons are accelerated in this direction. Since the floating gate is not located in this direction of the velocity vectors of the channel hot electrons, the resulting injection efficiency and the resulting write efficiency are far from being satisfactory. Consequently, it has been impossible to meet the demand for increasing a write speed and for decreasing write voltages.
In addition, the device shown in FIG. 14D increases data erasure (electron takeout) efficiency by sharpening the peripheral region of the floating gate 103. According to such a method, the efficiency is surely increased, but the region, from which the electrons are taken out, is adversely restricted to a narrow area. As a result, the current density is undesirably increased in such an area and the oxide film is more likely to be damaged.
Furthermore, in the prior art, if a mask cannot be satisfactorily aligned with the control gate 109 during the patterning of the control gate 109, then the positional relationship between the control gate 109 and the floating gate 103 is varied. As a result, an effective channel length cannot be precisely defined, thereby causing a large variation in resulting electric characteristics.